Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay

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Efficient Usage of QOS of Area Delay Power Efficient Carry Select Adder

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0778-0784

Low Power Area Efficient ROM Embedded SRAM Cache

Authors:M. SWATHI, D. NAGESHWAR RAO, D. SUDHAKAR

0785-0790

Design of Low Power Data Encoding Schemes Architectures to Reduce Power Dissipiation in Links on Network-On-Chip

Authors:K.LAXMI TIRUPATHAMMA, ANITHA PATIBANDLA

0791-0799

Implementation of Modified Booth Recoder Design for Add and Multiply

Authors:P. GURUMURTHY, D. VENKATARAMI REDDY, GUJJULA KOTI REDDY

0800-0807

Implementation of High Speed CSLA for Low Power Applications

Authors:SANDHI SAI KRISHNA, J. SREELATHA

0808-0812

BIST Technology for Fault Diagnosis in FPGA

Authors:SANGOJU SATHEESH, P. S. SUREKHA

0813-0815

Design and Implementation of 12 TAP FIR Filter

Authors:TIRUKOVELA RAKESH, A. SRINIVAS REDDY

0816-0820

Realization of Power Optimized OCP Bus Architecture for Network on Chip Applications

Authors:TALLA SINDHUJA, Y. GAYATRI

0821-0827

Implementation of Low Latency AES Architecture for High Speed Applications

Authors:NAREPALEPU KESHAV, A. HARISH

0828-0833